On a p-type semiconductor silicon substrate with low doping concentration, two N + regions with high doping concentration are fabricated by semiconductor lithography and diffusion process, and two electrodes are led out with metal aluminum as drain D and source s respectively. Then, a thin silicon dioxide (SiO2) insulating layer film is covered on the surface of the p-type semiconductor between the drain and the source, and an aluminum electrode is installed on the insulating layer film as the gate G. This constitutes an n-channel (NPN type) enhanced MOS transistor. Obviously, its grid is insulated from other electrodes. A and B shown in Figure 1-1 are its structure diagram and representative symbols respectively.

Similarly, using the same method above, two P + regions with high doping concentration are fabricated by semiconductor lithography and diffusion process on an n-type semiconductor silicon substrate with low doping concentration, and the same gate fabrication process above, a p-channel (PNP type) enhanced MOS transistor is prepared. The following figure shows the structure diagram and representative symbols of n-channel and p-channel MOS pipes respectively